* A new REX-like prefix that extends the number of addressable GPRs to 32 from 16. This only supports instructions that have one-byte opcodes or the 0f prefix, so recent GPR instructions like ADCX or BLSR aren't supported with this format, except.
* The EVEX prefix (used for AVX-512) is also extended to be usable for GPR instructions instead of just vector instructions. This allows three-address instructions to be defined.
* The EVEX prefix for GPR also has a dedicated bit for "do you want to set flags as a result of this instruction."
* New instructions that push/pop 2 GPRs at once
* New instructions that let you conditionally set flags (basically you can do OR/AND in the hardware flags, this sounds useful for compilers).
* New instructions for predicated loads.
* New 64-bit absolute jump instruction
* Also, implementation of the predicated stuff in AVX-512, but for 256-bit vectors. With this note:
> A “converged” version of Intel AVX10 with maximum vector lengths of 256 bits and 32-bit opmask registers will be supported across all Intel processors, while 512-bit vector registers and 64-bit opmasks will continue to be supported on some P-core processors.
* A new REX-like prefix that extends the number of addressable GPRs to 32 from 16. This only supports instructions that have one-byte opcodes or the 0f prefix, so recent GPR instructions like ADCX or BLSR aren't supported with this format, except.
* The EVEX prefix (used for AVX-512) is also extended to be usable for GPR instructions instead of just vector instructions. This allows three-address instructions to be defined.
* The EVEX prefix for GPR also has a dedicated bit for "do you want to set flags as a result of this instruction."
* New instructions that push/pop 2 GPRs at once
* New instructions that let you conditionally set flags (basically you can do OR/AND in the hardware flags, this sounds useful for compilers).
* New instructions for predicated loads.
* New 64-bit absolute jump instruction
* Also, implementation of the predicated stuff in AVX-512, but for 256-bit vectors. With this note:
> A “converged” version of Intel AVX10 with maximum vector lengths of 256 bits and 32-bit opmask registers will be supported across all Intel processors, while 512-bit vector registers and 64-bit opmasks will continue to be supported on some P-core processors.